1、国家重点研发计划项目：低功耗CMOS氧化物薄膜晶体管及其三维集成技术研究
2、国家科技重大专项：MCP、nweWLP封装设计优化与系统可靠性分析
3、973项目：20/14nm集成电路晶圆级三维集成制造的基础研究
4、973项目：半导体相变存储器
5、国家自然科学基金重点项目：高性能集成芯片容错互连架构
6、国家自然基金重点项目：面向机器人的集成柔性多物理量传感阵列及其信号处理关键技术研究
7、国家自然基金项目：面向SoC高温老化测试的靶向化矢量生成与测试调度方法研究
8、863项目：面向特定算法的阵列DSP的低功耗关键技术研究
9、广东省重点领域研发计划项目：可敏捷定制的智能视觉处理器及系统应用
10、广东省科技重大专项：集成电路设计EDA技术创新支撑平台
11、广东省科技重大专项子课题：SoC芯片测试验证技术、关键设备研发与产业化
12、广东省自然科学基金项目：面向SoC芯片WLTBI的测试矢量生成与测试调度方法研究
13、广东省自然科学基金项目：3D SRAM的可测性设计研究
14、广东省自然科学基金项目：基于博弈论的软件测试过程模型研究
15、深圳市学科布局项目：基于忆阻器的逻辑电路设计方法研究
16、深圳市学科布局项目：集成电路故障表征和测试向量生成关键问题研究
17、深港联合创新项目：Chiplet架构的集成优化设计技术研究
18、深圳市重点实验室提升计划项目：基于无线测试访问端口的芯片测试架构研究
19、深圳市产学研重大专项项目：面向晶圆表面缺陷的智能AOI系统
20、深圳市科技重大专项：基于Chiplet的智能芯片可靠性关键技术研究
1.A reconfigurable built-in self-test scheme for the evaluation circuits of digital SRAM-IMC architectures,IEEE Transactions on Very Large Scale Integration Systems(TVLSI), vol.34, no.1,2026, pp:280-293.
2.FNS-CATF-CAC: An effective crosstalk avoidance code to reduce the switching activity in TSV arrays, IEEE Trans. on Reliability, vol.74,no.3, 2025, pp:3856-3870.
3.A network-coding-based functional test method for routers in 3-D Mesh NoCs, IEEE Internet of Things Journal, vol.12, no.8, 2025, pp: 9940-9953.
4.Design of Highly Reliable 14T and 16T SRAM Cells Combined with Layout Harden Technique, IEEE Trans. on Device and Materials Reliability, vol.24, no. 3,September, 2024, pp:390-400.
5.An In-Array Build-In Self-Test Scheme for Embedded SRAM Array, IEEE Trans. on Circuits and Systems II: Express Briefs(TCAS-II), vol.71, no.8, August,2024,pp: 3935 - 3939.
6.An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations, IEEE Trans. on Circuits and Systems II: Express Briefs(TCAS-II) , vol.71, no.4, April, 2024, pp:2329-2333.
7.DyMFNS-CAC: An encoding mechanism to suppress the crosstalk and repair the hard faults in rectangular TSV arrays, IEEE Trans. on Reliability,vol.73,no.1，2024，March, pp:622-636.
8.The resistance analysis attack and security enhancement of the IMC LUT based on the complementary resistive switch cells, ACM Trans. on Design Automation of Electronic Systems (TODAES), vol.29, no.1, November, 2023, pp:10:1-10:21.
9.An area-efficient in-memory implementation method of arbitrary Boolean function based on SRAM array, IEEE Trans. on Computers, vol.72, no.12, 2023, pp: 3416-3430.
10.Mosaic-3C1S: A low overhead crosstalk suppression scheme for rectangular TSV Array,IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.42, no. 5,2023, pp:1380-1392.
11.An evaluation method of the anti-modeling-attack capability of PUFs, IEEE Trans. on Information Forensics & Security, vol.18 , no.3 , 2023, pp:1773 - 1788 .
12.Aglobal self-repair method for TSV arrays with adaptive FNS-CAC codec, IEEE Design & Test of Computers, vol.39, no.5, 2022, pp:26-33.
13.A new scheme of the low-cost multiple-node-upset-tolerant latch,IEEE Trans. on Device and Materials Reliability, vol.22, no.1,March, 2022, pp:50-58.
14.An enhancement of crosstalk avoidance code based on Fibonacci numberal system for through silicon vias, IEEE Transactions on Very Large Scale Integration Systems, vol.25, no.5, 2017, pp：1601-1610.
15. High-performance noninvasive side-channel attack resistant ECC coprocessor for GF(2m), IEEE Transactions on Industrial Electronics，vol.64, no.1, 2017, pp:.727-738
16.A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes, IEEE European Test Symposium (ETS), 2025.
17. A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions,IEEEAsian Test Symposium(ATS), 2024.
18. An anti-removal-attack hardware watermarking method based on polymorphic gates, IEEE International Conference on Computer AidedDesign (ICCAD) 2023.
19. A Modeling Attack on the sub-threshold current array PUF, IEEEInternational Symposium on Hardware Oriented Security and Trust,(HOST), 2022.
20. The security enhancement techniques of the double-layer PUF against the ANN-based modeling attack, IEEE International Test Conference (ITC),2021.
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