Brief Introduction：
Engaged in teaching and research in the field of integrated circuits and systems for a long time.
Has undertaken over twenty national, provincial, municipal, and industrial research projects; published more than two hundred academic papers in journals and conferences such as IEEE TVLSI, IEEE TIE, IEEE DATE, and IEEE ATS; IEEE member; holds multiple authorized invention patents; has received provincial and ministerial-level scientific and technological awards and the best paper award at IEEE academic conferences; served as an editorial board member for journals like Scientific Reports; served as the TPC member of conferences such as IEEE ITC-HOST and IEEE ATS.
Research Interests: IC design；Design for Testability/Reliability/Security of IC；Dependable Computing
Requirements for the PhD. and Master Students：
1、Majors：Electronics、Computer、Communication、Cybernetics、Instrumentation、Signal Processing etc.
2、Capability of English/Math：Good.
3、Capability of Research and Engineering：Good.
4、The most important point ：Strong interest in research.
Projects:
1、National Key R&D Program Project: Research on Low Power CMOS Oxide Thin Film Transistor and Its 3D Integration Technology
2、National Science and Technology Major Project: MCP, nweWLP Packaging Design Optimization and System Reliability Analysis
3、National Key Basic Research Project: Research on 20/14nm Integrated Circuit Wafer Level 3D Integrated Manufacturing
4、National Key Basic Research Project: Semiconductor Phase Change Memory
5、Key Project of National Natural Science Foundation of China: High Performance Integrated Chip Fault Tolerant Interconnection Architecture
6、Key Project of National Natural Science Foundation of China: Research on Key Technologies of Integrated Flexible Multi physics Sensing Array and Signal Processing for Robots
7、National Natural Science Foundation Project: Research on Targeted Vector Generation and Test Scheduling Method for SoC High Temperature Aging Testing
8、863 Project: Research on Low Power Key Technologies of Array DSP for Specific Algorithms
9、Key R&D Program Project in Guangdong Province: Agile Customizable Intelligent Visual Processor and System Applications
10、Guangdong Province Major Science and Technology Project: Integrated Circuit Design EDA Technology Innovation Support Platform
11、Sub project of Guangdong Province's Major Science and Technology Special Project: SoC Chip Testing and Verification Technology, Key Equipment Research and Industrialization
12、Guangdong Provincial Natural Science Foundation Project: Research on Test Vector Generation and Test Scheduling Method for SoC Chip WLTBI
13、Guangdong Provincial Natural Science Foundation Project: Research on Testability Design of 3D SRAM
14、Guangdong Natural Science Foundation Project: Research on Software Testing Process Model Based on Game Theory
15、Key Basic Research Project of Shenzhen: Research on Logic Circuit Design Method Based on Memristor
16、Key Basic Research Project of Shenzhen: Research on Key Technologies of Integrated Circuit Fault Characterization and Test Vector Generation
17、Shenzhen Hong Kong Joint Innovation Project: Research on Integrated Optimization Design Technology of Chiplet Architecture
18、Shenzhen Key Laboratory Enhancement Plan Project: Research on Chip Testing Architecture Based on Wireless Test Access Port
19、Shenzhen Industry University Research Major Special Project: Intelligent AOI System for Wafer Surface Defects
20、Shenzhen Major Science and Technology Project: Research on Key Technologies for Reliability of Intelligent Chips Based on Chiplets
Recent publications:
1. A reconfigurable built-in self-test scheme for the evaluation circuits of digital SRAM-IMC architectures, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.34, no.1, 2026, pp:280-293.
2. FNS-CATF-CAC: An effective crosstalk avoidance code to reduce the switching activity in TSV arrays, IEEE Trans. on Reliability, vol.74, no.3, 2025, pp:3856-3870.
3. A network-coding-based functional test method for routers in 3-D Mesh NoCs, IEEE Internet of Things Journal, vol.12, no.8, 2025, pp: 9940-9953.
4. Design of Highly Reliable 14T and 16T SRAM Cells Combined with Layout Harden Technique, IEEE Trans. on Device and Materials Reliability, vol.24, no. 3, September, 2024, pp:390-400.
5. An In-Array Build-In Self-Test Scheme for Embedded SRAM Array, IEEE Trans. on Circuits and Systems II: Express Briefs (TCAS-II), vol.71, no.8, August, 2024, pp: 3935 - 3939.
6. An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations, IEEE Trans. on Circuits and Systems II : Express Briefs (TCAS-II) , vol.71, no.4, April, 2024, pp:2329-2333.
7. DyMFNS-CAC: An encoding mechanism to suppress the crosstalk and repair the hard faults in rectangular TSV arrays, IEEE Trans. on Reliability, vol.73, no.1，2024，March, pp:622-636.
8. The resistance analysis attack and security enhancement of the IMC LUT based on the complementary resistive switch cells, ACM Trans. on Design Automation of Electronic Systems (TODAES), vol.29, no.1, November, 2023, pp:10:1-10:21.
9. An area-efficient in-memory implementation method of arbitrary Boolean function based on SRAM array, IEEE Trans. on Computers, vol.72, no.12, 2023, pp: 3416-3430.
10. Mosaic-3C1S: A low overhead crosstalk suppression scheme for rectangular TSV Array, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.42, no. 5, 2023, pp:1380-1392.
11. An evaluation method of the anti-modeling-attack capability of PUFs, IEEE Trans. on Information Forensics & Security, vol.18 , no.3 , 2023, pp:1773 - 1788 .
12. A global self-repair method for TSV arrays with adaptive FNS-CAC codec, IEEE Design & Test of Computers, vol.39, no.5, 2022, pp:26-33.
13. A new scheme of the low-cost multiple-node-upset-tolerant latch, IEEE Trans. on Device and Materials Reliability, vol.22, no. 1, March, 2022, pp:50-58.
14. An enhancement of crosstalk avoidance code based on Fibonacci numberal system for through silicon vias, IEEE Transactions on Very Large Scale Integration Systems, vol.25, no.5, 2017, pp：1601-1610.
15. High-performance noninvasive side-channel attack resistant ECC coprocessor for GF(2m), IEEE Transactions on Industrial Electronics，vol.64, no.1, 2017, pp:.727-738
16.A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes, IEEE European Test Symposium (ETS), 2025.
17. A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions, IEEE Asian Test Symposium(ATS), 2024.
18. An anti-removal-attack hardware watermarking method based on polymorphic gates, IEEE International Conference on Computer Aided Design (ICCAD) 2023.
19. A Modeling Attack on the sub-threshold current array PUF, IEEE International Symposium on Hardware Oriented Security and Trust, (HOST), 2022.
20. The security enhancement techniques of the double-layer PUF against the ANN-based modeling attack, IEEE International Test Conference (ITC), 2021.
