• 李崇仁

  • 职称:教授(兼职教师)
  • 职务:测试实验室主任
  • Email:licr@pkusz.edu.cn
  • 个人主页:http://tiger.ee.nctu.edu.tw/cllee/cll.htm
研究方向:数字与模拟电路设计;SoC应用系统设计;数字、模拟电路测试;SoC测试与可测试性设计。
导师与研究领域、方向:

    台湾大学学士、美国卡内基大学硕士, 博士。台湾交通大学电子工程系副教授,教授。从事半导体器件、 数字电路与系统、模拟电路、SoC 测试与可测试设计诸领域之教学研究。指导超过百位硕士生、三十位博士生毕业,发表论文三百余篇。为该校超大型集成电路研究群之创始人。曾任该校半导体中心、次微米专业人才培训中心主任。曾组织台湾各大学从事测试研究教授,开发一超大型集成电路测试课程。曾任 IEEE Asian Test Technology Technical Committee 委员、学术期刊 J. of Electronic Testing, Theory, and Application 编辑委员。北京大学访问教授,北大深圳研究生院访问教授: 教授混合信号电路测试课程; 指导研究生硕士论文研究。分別受邀于2004年、2006年中国测试会议作受邀讲席演讲: “混合电路之测试”、“SoC 低成本低功耗之测试”. 2009年起担任北京大学深圳研究生院专职教授。拟从事科研研究项目:1) 建立 SoC 测试与可测试性设计架构与环境;2) 显示器推动电路之设计;3) 时脉与波形产生器电路系统之设计;4) 语音辨识与合成电路设计研究。

近5年来取得的主要成果:
1. M.S. Wu, C.L. Lee, and J.E. Chen, “A Squareware Test Scheme for Detection Crosstalk Faults in Boundary Scan Environment for Deep Submicron VLSI”, IEEE Design & Test of Computers, Vol 22, pp160-169, 2005
2. S. M. Li, C.L. Lee, C,C. Su and J.E. Chen, “Oscillation Ring Based Interconnect Test Scheme for SOC”, Proc. Asian Pacific Design Automation Conf.,  pp184-187, 2005.
3. S.P. Lin, C.L. Lee, and J.E. Chen,  “A Scan Matrix Design for Low Power Scan-Based Test”, Asian Test Symposium, 2005
4. S.P. Lin, C.L. Lee, and J.E. Chen, “Adaptive Encoding Scheme for Test Volume/Time Reduction in Soc Scan Testing”, Asian Test Symposium, 2005
5. S.P. Lin, C.L. Lee, and J.E. Chen, “A Cocktail Approach on Random Access Scan toward Low Power and High Efficiency Test”,  ICCAD, 2005
6. C.H. Kao, C.S. Lai, and C.L. Lee, “Oxide Grown on Polycrystal Silicon by Rapid Thermal Oxidation in N2O”, J. of Electrochemical Society, Vol.153, No2, 2006.
7. S.P. Lin, C.L. Lee, et al, “A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs”, Int. Test Conference, 2006
8. C.H. Kao, C.S. Lai, and C.L. Lee, “Polarity Asymmetry of Polyoxide Grown on Phosphorus in-situ Doped Polysilicon”, J. of Electrochemical Society, Vol.153, No9, 2006.
9. K. S.-M. Li, C. Su, Y.-M. Chang, C.-L. Lee, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,”IEEE Trans. Computer-Aided Design, Vol. 25, No. 11, 2006.
10. S.P. Lin, C.L. Lee, and J.E. Chen, "Low Power Test Compression for Multiple Scan Chain Designs”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 7, p.p.767-776 , 2007.
11. K. S.-M. Li, Y. –W Chang, C.-L. Lee, C. Su and J.-E Chen, “Multilevel Full-Chip Routing With Testability and Yield Enhancement,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 9, 2007.
12. C. -H. Kao, C.-S. Lai and C. -L. Lee “Electrical and Reliability Improvement in Polyoxide by Fluorine Implantation”, J. of Electrochemical Society, Vol.154, No. 4, 2007.
13. W. Hu, C. -L. Lee, and X. Wang “Fast Frequency Acquisition Phase-Frequency Detector with Zero Blind Zone in PLL”, Electronics Letters, Vol. 13, no. 18, p.p. 1018 – 1020, 2007
14. W.B. Hu, C.L. Lee, and X. Wang, “An Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer”, DELTA 2008, 2008
15. J. Ruan, and C.L. Lee, “A Fast Two-Stage Sample-and-Hold Amplifier for ADC Application”,DELTA 2008, May 2008
16. L.R. Wang, S.J. Jou, and C.L. Lee, “A Well-Structured Modified Booth Multiplier Design”,VLSI-DAT 2008, April 2008.
17. L.R. Wang, S.J. Jou, and C.L. Lee, “A Reconfigurable Mac Architecture Implemented with Mixed-Vt Standard Cell Library", ISCAS 2008, May 2008.
18. S. P. Lin, C. L. Lee, J. J. Chen, K.L. Luo, and W. C. Wu, “Column-Addressable Multiple Scan Architecture for Low Power Testing and Delay Testing”, ITSW 2009, March 2009
19. K.S.-M. Li, C.L. Lee, J.E. Chen, and C.C. Su, “"A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus", IEEE Trans. on VLSI, Vol 17, pp306-311,2009