• 焦海龙

  • 职称:副教授
  • 电话:0755-26035580;办公室:A-320
  • Email:jiaohl@pkusz.edu.cn
  • 实验室网站:http://web.pkusz.edu.cn/VLSI
研究方向:低功耗高可靠性超大规模集成电路与系统设计

焦海龙,博士,北京大学深圳研究生院副教授。2004年于山东大学获得电子信息科学与技术专业学士学位,2008年于中国科学院微电子研究所获得微电子学与固体电子学硕士学位,2012年于香港科技大学获得电子及计算机工程学博士学位。2013年9月加入荷兰埃因霍温理工大学电子工程系,任职Tenure-track Assistant Professor,2016年9月获得终身教职。2015年2月起,兼任比利时鲁汶微电子中心(IMEC)三维集成部门访问研究员。2017年1月全职加入北京大学深圳研究生院信息工程学院。焦海龙博士现任Elsevier Microelectronics Journal (MEJ)及World Scientific Journal of Circuits, Systems, and Computers (JCSC)编委,并长期担任如ISVLSI, SOCC, ASP-DAC等多个IEEE/ACM国际会议的技术委员会成员。

焦海龙博士的主要研究方向为低功耗高可靠性超大规模集成电路与系统设计,重点关注容错系统设计、近似计算、机器学习在超大规模集成电路中的应用、三维集成电路设计及测试、碳基电子学等。已在相关领域发表国际期刊及会议论文40余篇,曾获2012年IEEE International SoC Design Conference 的SOC Design Group Award以及2014年IEEE International Conference on Microelectronics的Best Paper Award。

 

目前承担的主要科研项目:

 

曾担任荷兰自然科学基金项目Wearable Brainwave Processing Platform (BrainWave)第一负责人,美国SRC项目QoS-Adequate Baseband Radio Processing (QoS-AB)及欧盟项目RESilient Integrated SysTems (RESIST)共同负责人。

 

主要研究成果:

  • 书籍章节
  • 1、H. Jiao and V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,” VLSI-SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258-290, 2012, ISBN 978-3-642-28565-3.
  • 期刊论文 (*通讯作者)
  • 1、H. Jiao, R. Wang, and Y. He, “Crosstalk-Noise-Aware Bus Coding with Low-Power Ground-Gated Repeaters,” Wiley International Journal of Circuit Theory and Applications, 2017.
  • 2、Y. Sun, W. He, Z. Mao, H. Jiao*, and V. Kursun, “A High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes,” IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 1, pp. 20-31, March 2017.
  • 3、H. Jiao, Y. Qiu, and V. Kursun, “Variability-Aware 7T SRAM Circuit with Low Leakage High Data Stability SLEEP Mode,” Elsevier Integration, the VLSI Journal, Vol. 53, pp. 68-79, March 2016.
  • 4、H. Jiao, Y. Qiu, and V. Kursun, “Low Power and Robust Memory Circuits with Asymmetrical Ground Gating,” Elsevier Microelectronics Journal, Vol. 48, pp. 109-119, February 2016.
  • 5、S. M. Salahuddin, H. Jiao, and V. Kursun, “FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability,” Transactions on Electrical and Electronic Materials, Vol. 16, No. 6, pp. 293-302, December 2015.
  • 6、Y. Sun, H. Jiao, and V. Kursun, “A Novel Robust and Low-Leakage SRAM Cell with Nine Carbon Nanotube Transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
  • 7、H. Jiao and V. Kursun, “Mode Transition Timing and Energy Overhead Analysis in Noise-Aware MTCMOS Circuits,” Elsevier Microelectronics Journal, Vol. 45, No. 8, pp. 1125-1131, August 2014.
  • 8、H. Jiao and V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533-545, March 2013.
  • 9、H. Jiao and V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 741-745, April 2012.
  • 10、H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 763-773, May 2011.
  • 11、H. Jiao and V. Kursun, “Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias,” World Scientific Journal of Circuits, Systems, and Computers (Special Issue on Green Integrated Circuits and Systems, Invited Paper), Vol. 20, No. 1, pp. 125-145, February 2011.
  • 12、H. Jiao and V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 2053-2065, August 2010.
  • 13、H. Jiao and V. Kursun, “Low-Leakage and Compact Registers with Easy-Sleep Mode,” ASP Journal of Low Power Electronics, Vol. 6, No. 2, pp. 263-279, August 2010.
  • 14、H. Jiao, L. Chen, Z. Li, Q. Yang, and T. Ye, “OPC Reuse Based on A Reduced Standard Cell Library,” IOP Journal of Semiconductors, Vol. 29, No. 5, pp. 1016-1021, May 2008.

 

  • 代表性国际会议论文
  • 1、M. van Leussen, J. Huisken, L. Wang, H. Jiao, and J. Pineda de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017.
  • 2、H. Ahmadi Balef, H. Jiao, J. Pineda de Gyvez, and K. Goossens, “An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 209-214, March 2017.
  • 3、H. Jiao, Y. Qiu, and V. Kursun, “Variations-Tolerant 9T SRAM Circuit with Robust and Low Leakage SLEEP Mode,” Proceedings of the IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2016.
  • 4、E. J. Marinissen, T. McLaurin, and H. Jiao, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,” Proceedings of the IEEE European Test Symposium (ETS), May 2016.
  • 5、S. Hamdioui, L. Xie, H. A. Du Nguyen, M. Taouil, K. Bertels, H. Corporaal, H. Jiao, F. Catthoor, D. Wouters, L. Eike, and J. van Lunteren, “Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 1718-1725, March 2015.
  • 6、Y. Sun, H. Jiao, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,” Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014 (Best Paper Award).
  • 7、H. Jiao and V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 52-57, August 2013.
  • 8、S. M. Salahuddin, H. Jiao, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 353-358, March 2013.
  • 9、H. Jiao and V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 466-469, November 2012 (SoC Design Group Award).
  • 10、H. Jiao and V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,” Proceedings of the IEEE International SoC Conference (SOCC), pp. 365-370, September 2011.
  •  
  • 发明专利
  • 1、V. Kursun, H. Zhu, and H. Jiao, “静态随机访问存储器及其控制方法,” Chinese Patent, CN201110359652.0, December 3, 2014.
  • 2、V. Kursun, S. M. Salahuddin, and H. Jiao, “具有非对称晶体管的静态随机访问存储器及其控制方法,” Chinese Patent, CN201310076418.6, January 20, 2016. 

 

对计划招收研究生的基本要求:

1.  Self-motivated(成功需要的是你个人的追逐,而非导师的鞭策);

2.  卓越的逻辑思维能力及动手能力;

3.  良好的英语听说读写能力;

实验室关注同学们的个人发展,致力于培养同学们成为具有独立研究能力及独立工程开发能力的科研工作者或者工程师。实验室同时将尽力为同学提供芯片tapeout机会(65-nm/40-nm/28-nm CMOS工艺),详情参见实验室网页 http://web.pkusz.edu.cn/VLSI/