Cadence北京研发中心招聘信息

2012-08-24 23:01:46

 

Cadence 2012 Job Vacancies

 

 

Cadencewww.cadence.com是全球领先的EDA (Electronic Design Automation)软件开发商以及电子设计自动化解决方案提供商.我们的产品涵盖了电子设计的整个流程,包括系统级设计,功能验证,IC综合及布局布线,模拟、混合信号及射频IC设计,全定制集成电路设计,IC物理验证,PCB设计和硬件仿真建模等。全球知名半导体与电子系统公司均将Cadence软件作为其全球设计的标准。

 

Cadence北京研发中心成立于2003, 现位于海淀区海淀东三街2号欧美汇大厦,主要协同美国总部共同研发Virtuoso全定制设计平台及其多模式仿真 (multi-mode simulation) 产品。 Virtuoso全定制设计平台是用于快速、硅精度设计的综合系统。Virtuoso平台包括:业界唯一的规格驱动的环境;使用通用语法、模型和方程式的多模式仿真;快速版图设计,用于0.18微米以下工艺的先进硅分析和全芯片混合信号集成仿真环境。使用该平台,设计团队可以用从1微米到45纳米的工艺迅速、准确、按时地设计出硅片.

 

我们正在寻找软件研发工程师产品测试工程师,欢迎微电子,电子,计算机,软件工程,数学及相关专业应届毕业硕士/博士加入我们!

 

如有兴趣请投递简历至 job_china@cadence.com,并标注你申请的职位名称。

对职位有任何疑问,也可发邮件至该信箱,我们HR同事会及时给你回复并尽快安排面试。

 

 

 

Who we are looking for?

 

Cadence Beijing Intern

 

1. PV (产品验证) Intern for Circuit Simulation (Location: BJ)
    Need to work full-time for more than 6 months
Position Description:
1.Work together with a group of professionals on a variety of PV/QA projects to enhance circuit simulation product quality.

Requirements:
1.Students who are pursuing master's degree in Microelectronics or EE.
2.Customer IC design experience.
3.UNIX/Linux experience.

If you have interest, PLS send your CV to job_china@cadence.com

 

Cadence Beijing R&D

 

1. Senior Software Engineer for SPICE Simulator   (Location: BJ)

 

Position Description:
1. The position is for analog circuit simulation engineer responsible for designing, implementing and maintaining SPICE-like circuit simulation software for use with analog, RF and mixed signal circuit simulators.

2.  The engineer will be responsible for leading multiple development efforts through the development process, including writing specifications based on marketing and product requirements, designing and implementing product improvements and fixes, and working with a cross-functional team to ensure the software is tested, integrated and documented.

Requirements:


1. Skilled in C/C++ programming, familiar with development under Linux/Unix environment;
2. Well understanding on matrix solver & mathematic calculation;
3. Be familiar with Analog-signal design is a plus;
4. Good English communication skill both verbally and writing;
5. Good problem solving skill and team work spirit;

If you have interest, PLS send your CV to job_china@cadence.com

 

2. Senior Developer (Location: BJ)

 

Position Description:

1.The positions are for a developer who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells.

 

Requirements:

 

1.The candidates should have experiences in developing EDA software.  

2.Must be proficient in C, C++, TCL, and development in Linux/Unix.

3.Knowledge on semiconductor device is strong plus.

4.Experience with SPICE or SPICE-like circuit simulation is important.   

5.Knowledge of Verilog and VHDL is also highly desirable.   

6.The ideal candidate would have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows. 

7.Minimum Education Required / Minimum Experience Required : Master or Ph.D. in MS, EE, CS, Math or Physics

If you have interest, PLS send your CV to job_china@cadence.com

 

 

3. Product Verification Engineer (Location: BJ)

 

Position Description:

1.The positions are for a PV who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells.

 

Requirements:

 

1.The candidates should have experiences in developing EDA software.  

2.Must be proficient in C, C++, TCL, and development in Linux/Unix.

3.Knowledge on semiconductor device is strong plus.

4.Experience with SPICE or SPICE-like circuit simulation is important.   

5.Knowledge of Verilog and VHDL is also highly desirable.   

6.The ideal candidate would have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows. 

7.Minimum Education Required / Minimum Experience Required : Master or Ph.D. in MS, EE, CS, Math or Physics

If you have interest, PLS send your CV to job_china@cadence.com

 

4. Senior Software Engineer for Fastspice Simulator   (Location: BJ)

 

Position Description   

1.Maintain and develop Cadence fastspice simulator.

2.Be responsible for writing specifications, designing and implementing product enhancements and fixes.

3.Needs to work with other global R&D teams..  

  

Position Requirements  

1.Education requirement: Master or Ph.D. in EE/CS/related research area.

2.Must be skilled in C/C++ programming, familiar with development under Linux/Unix environment.

3.Strong background in numerical computation and programming.

4.Knowledge of Analog Mixed-signal design and semiconductor device is a strong plus.

5.Good English communication skills both verbally and in writing.

If you have interest, PLS send your CV to job_china@cadence.com

 

 

5. Software Engineer for RF simulator (Location: BJ)

 

Position Description:    .

Develop and maintain Cadence state-of-art RF simulation product.

Be able to work with a cross-functional team to ensure the software is tested, integrated and documented

                                                       

Position Requirements:          

 

Required:

1.Strong command of Cadence SKILL language and development

2.2-5 years industry experience (EDA, foundry or IC design)

 

Preferred:

1.Experience developing custom libraries/PDKs in Virtuoso

2.Exposure to integration of 3rd party tools within Virtuoso

3.Experience in Analog/RF design is a plus.

4.Education Requirement: Master in EE, CS, or related.

5.C/C++ Unix development a plus.

6.Good command in written and oral English

If you have interest, PLS send your CV to job_china@cadence.com

 

 

6. Senior Software Engineer for Virtuoso ADE GXL (Location: BJ)

 

Position Description:

1.Dealing with manufacturing variation is becoming an increasingly important aspect of the custom digital and analog circuit design process. Virtuoso ADE GXL is a software tool for designers that offers statistical analysis, yield improvement, and design optimization capabilities to address this growing problem. We are seeing a talented software developer with a strong background in statistical analysis, data mining and modeling.  
       

Position Requirements:   

1.Strong background in statistical analysis, data mining, and modeling

2.Demonstrated proficiency in C++ and general software development skills

3.Master in Computer Science or Electrical Engineering required, PhD preferred.

4.Excellent communication skill in both mandarin and English.

5.Working knowledge of Matlab a plus.

6.Experience with Cadence Virtuoso or analog circuit design a plus. 

If you have interest, PLS send your CV to job_china@cadence.com

 

7.Senior Software Engineer (Location: BJ)

 

Position Description:

1.Develop, enhance and maintain mixed signal circuit simulator which support Verilog, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS and SystemVerilog.

  

Position Requirements:   

1.Familiar with Spice, Verilog, Verilog-A, Verilog-AMS, VHDL-AMS language

2.Skilled in C++ programming, familiar with development under Linux/Unix environment.

3.Analog circuit or digital simulator development experiences

4.Be familiar with Analog Mixed-signal design is a plus

5.EE or CS Master degree with at least 2 years related working experience or above

If you have interest, PLS send your CV to job_china@cadence.com

 

 

8. Software Engineer Virtuoso GUI

 

Position Description:

1.Candidate will be involved in Development, enhancement and maintain Cadence Virtuoso platform.

2.Candidate will be involved in GUI integrating Cadence simulation product into Cadence Virtuoso platform.

 

Position Requirements:   

1.BS in CS/EE or similar level of expertise with at least 2 years of working experience.

2.Candidate must have some coding experience. C, C++ are must. QT, STL would be a plus.

3.Better to have experience of using SKILL(Cadence programming language), OpenAccess

4.Highly desirable if the candidate has some GUI coding experience

5.The candidate must some EE knowledge about analog design. Good if the candidate is familiar with Cadence Virtuoso platform.

6.English verbal and written

If you have interest, PLS send your CV to job_china@cadence.com

 

9. Software Configuration Management (CM) Engineer (Location: BJ)

 

Job Description:

 This position involves managing daily software build, test, and release processes, and   

 configuration management support for other cross functional teams. The responsibility also

 includes maintaining and enhancing the existing automation systems, designing and

 developing new automation systems, software integration, and project management.

 

Position Requirements  

1.Computer Science or Engineering Bachelor degree.

2.Good programming background.

3.Experience of Unix/Linux system.

4.Good problem solving & analysis skills.

5.Good interpersonal, verbal, and written communication skills.

6.Fast and self learner.

If you have interest, PLS send your CV to job_china@cadence.com

 

 

10. Senior Software  Engineer for Verilog-A simulator development(Location: BJ)

 

Position Description:

1.Develop, enhance and maintain Verilog-A simulator.

 

Position Requirements:   

1.Familiar with Spice, Verilog-A, Verilog-AMS language

2.Skilled in C++ programming, familiar with development under Linux/Unix environment.

3.Analog circuit or digital simulator development experiences.

4.Well understanding on circuit simulation technology, including MNA, dc, tran method.

5.Good mathematic background & knowledge.

6.Be familiar with Analog Mixed-signal design is a plus

7.EE or CS Master degree of above

If you have interest, PLS send your CV to job_china@cadence.com